[ale] Dual core CPUs in cluster?

[James P. Kinney III]

On Wed, 2005-04-27 at 18:26 -0400, Jeffrey B. Layton wrote:
> James P. Kinney III wrote:
> 
> >However, the datasheets I have looked at show something I don't like,
> >shared L1 and L2 cache. I don't recall if this is entirely accurate or
> >not or if it was a "special" version. It seems to me that a shared L1 is
> >asking for trouble. Shared L2 (the deepest data cache) would also be a
> >problem as both core would not be working on the same data thus
> >requiring a page out.
> >  
> >
> 
>    For the AMD dual-core the L1 and L2 caches are all separate.
> There is a cross-bar in the chip though to help with memory
> access requests, etc.
Good! Thanks for the info. I need to read more closely (or at least
before 1 am).

>    The Intel dual-cores are the same but don't have a crossbar
> to help things. I've also read some rumors that in the next
> generation, Intel will be adding a L3 cache and may have a
> combined L2 cache across cores. If you can code for that
> kind of architecture then codes that need to communicate
> from core to core can just used the L2 to pass data. Theoretically
> a good idea, but probably difficult to code for.
> 
> 
> Jeff
> 
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James P. Kinney III          \Changing the mobile computing world/
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GPG ID: 829C6CA7 James P. Kinney III (M.S. Physics)
<jkinney at localnetsolutions.com>
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