[ale] mosix clusters?

[Jeff Hubbs]

Dow -

Look, man, why don't you just admit that you're running Quake and let it
go at that?? :-)

But, seriously, folks, I guess this is a case of what I was speculating
about.  Maybe once I get past Mosix "Node 0" I should experiment with
that and see.

- Jeff



On Mon, 2002-06-24 at 11:31, Dow Hurst wrote:
> On our SGI Origin 200 servers with two processors we can get better 
> efficiency by running three computational jobs instead of two.  The 
> total time is greater than two jobs but less than three sequential jobs. 
>  Each job shows 68% of the CPU while running.  These are FPU based 
> MonteCarlo based algorithms for molecular conformational analysis.
> Dow
> 
> 
> Jeff Hubbs wrote:
> 
> >On Sun, 2002-06-23 at 23:12, Joseph A Knapka wrote:
> >  
> >
> >>Jeff Hubbs wrote:
> >>    
> >>
> >>>To revisit a bit, you'd need to know if, on a given 1-CPU machine, two
> >>>SAH WUs run at once is faster than, slower than, or as fast as two WUs
> >>>run end-to-end in the typical fashion.  If it's slower, then there is
> >>>absolutely nothing to be gained by running more SAH WUs at once than you
> >>>have CPUs.  My experience suggests that it would be slower, implying
> >>>that one instance per CPU is OPTIMAL; I say this because on a 2-CPU
> >>>machine, both CPUs get saturated, which tells me that memory I/O is not
> >>>an issue.  One instance per CPU is no different than what I do on every
> >>>machine I can get my hands on, Mosix-less.
> >>>      
> >>>
> >>Surely it is impossible for two WUs to run simultaneously on
> >>a single-CPU box in less time than they would run serially,
> >>since in the simultaneous case both WUs would presumably
> >>always be runnable, and thus you'd have context-switch
> >>overhead that wouldn't be present if single WU were the
> >>only runnable process on the box.
> >>
> >>    
> >>
> >
> >Joe -
> >
> >That's what I would assume as well.  I don't have the 'fu to know just
> >how much context-switching overhead that would entail.  I do wonder,
> >though, if there might be some "sweet spot" that takes advantage of the
> >way the processes use the CPU/mobo architecture, what with instruction
> >pipelining and L1/L2 cache.  
> >
> >
> >---
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> >
> >
> >  
> >



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